Mux-and-DeMux-Design

📌 Multiplexer and Demultiplexer Design using Verilog 📖 Overview

This project demonstrates the design and simulation of a 2:1 Multiplexer (MUX) and a 1:2 Demultiplexer (DEMUX) using Verilog HDL. These are fundamental combinational circuits widely used in digital systems for data selection and routing.

The functionality is verified using waveform simulation on EDA Playground. 🎯 Objectives Design a 2:1 Multiplexer using Verilog Design a 1:2 Demultiplexer using Verilog Simulate both circuits and verify outputs Understand combinational logic behavior ⚙️ Technologies Used Verilog HDL EDA Playground (Simulation) Icarus Verilog / ModelSim

🚀 Live Simulation

Click below to view and run the simulation:

👉 ▶ Run this project on EDA Playground

Note: Click Run in EDA Playground to see the waveform output.

Steps:

1. Open the link
2. Click Run ▶
3. View waveform in EPWave
   ✔️ Observations When S = 0, MUX output follows I0 When S = 1, MUX output follows I1 DEMUX correctly routes input to Y0 or Y1 based on select line 🔍 Features Simple combinational logic design Easy to understand and simulate Uses conditional (assign) statements Extendable to higher-order circuits 🚀 Future Enhancements Implement 4:1 and 8:1 MUX Gate-level modeling FPGA implementation Add timing analysis 👩‍💻 Author

Geetha MK Electronics and Communication Engineering Student